1. Field of the Invention
The present invention generally relates to electrical antifuses and, more particularly, to antifuses which are compatible with current CMOS manufacturing processes and which can be programmed easily, rapidly and with high reliability to alter electrical characteristics thereof by a readily detectable margin.
2. Description of the Prior Art
The use of fuses and antifuses in integrated circuits has become widespread in recent years, particularly for substituting spare circuits or circuit elements for defective circuits and circuit elements in order to increase manufacturing yield and avoid economic losses due to costs incurred in fabricating an integrated circuit which may not meet required specifications. Further, fuses and antifuses have been used to tailor circuit parameters for optimal performance and to electronically identify chips such as radio frequency (RF) chip identification. In recent years, fuses, in which resistance is increased during programming, and antifuses, in which resistance is decreased during programming, have also found applications in structures of choice for so-called “write once read many (WORM)” non-volatile memory cells.
This latter application, in particular, has imposed some stringent requirements on the size and structure of fuses and antifuses and on the process of fabricating such structures and the manner in which such fuses and antifuses may be programmed. This is particularly so since such applications often require numerically large arrays of fuses and/or antifuses integrated with circuits which are formed in accordance with other technologies and which may be compromised by aspects of the programming process, particularly if performed with desirable rapidity over part or all of the array. In general, antifuses are considered to be preferable to fuse structures since they can be fabricated at smaller dimensions, thus allowing numerically larger arrays in a given chip area.
However, at the present state of the art, antifuses have numerous serious drawbacks. For example, antifuses have been fabricated as a sandwich of two regions of conductive material separated by an insulating layer which can be broken down by a current developed by a suitably high programming voltage (e.g. typically above 6 volts). However, a severe trade-off exists between the level of the required high programming voltage and the potential for damage to other circuits on the chip and reliable operation of the programmed antifuse at lower voltages (e.g. about 5 volts or less). Good reproducibility of programming results is also difficult to achieve. Further, the dielectric layer presents substantial capacitance which slows circuit operation, particularly where numerous, unprogrammed antifuses exist on a single word or bit line. Further, a low pressure chemical vapor deposition process, which is required to deposit the dielectric with high uniformity in the film composition and thickness, may induce the formation of so-called hillocks in the first metallic layer.
Another antifuse structure comprises an interlayer of amorphous silicon (having a thickness about twenty times greater or more than the dielectric sandwich described above for comparable programming voltages) sandwiched between first and second layers of metal. However, such structures have extremely high leakage currents which can cause serious problems of controllability of programming and, in turn, severe storage time degradation problems. Additionally, such structures may be prone to crack propagation and continuity failure over long periods of use.